The present disclosure relates to small-size, low-cost solid-state image sensing devices, and to methods for fabricating the same.
In recent years, as a solid-state image sensing device, for example, Japanese Patent Publication No. 2000-224495 has disclosed a solid state image sensor as illustrated in FIG. 10 in which a sensor block 151 and a signal processing block 152 are integrated into a same semiconductor substrate in order to reduce the size and the power consumption and to increase the signal processing speed of the solid state image sensor. Moreover, based on the configuration, in order to further reduce the size and to further increase the speed, a configuration referred to as system in package (SIP) has been reported, wherein a solid-state image sensing element and a plurality of chips serving as peripheral circuits of the solid-state image sensing element are integrally mounted as a semiconductor module.
For example, Japanese Patent Publication No. H11-261044 (page 7, FIG. 1) discloses a configuration as illustrated in FIG. 11 in which a solid-state image sensing element 112 and a peripheral circuit element 111 are mounted by being stacked, and the solid-state image sensing element 112 is electrically connected to the peripheral circuit element 111 via a multilayer substrate 110.
Moreover, for example, Japanese Patent Publication No. 2006-49361 discloses a configuration as illustrated in FIG. 12 in which a back face irradiation type CMOS image sensor chip 154 is mounted by being stacked on a signal processing chip 153 via microbumps 155, where signals are input/output via the signal processing chip 153.
Furthermore, Japanese Patent Publication No. 2004-146728 (page 9, FIG. 1) discloses a configuration of a general semiconductor device which is not a solid-state image sensing device, the size of the general semiconductor device being reduced by the chip on chip (COC) technology of connecting main faces of different semiconductor elements to each other with the main faces facing each other.